1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device with static memory cells.
2. Description of the Background Art
An SRAM (Static Random Access Memory), which is a representative semiconductor memory device, is an RAM that does not require a refresh operation for retaining stored data. A memory cell of the SRAM is structured such that a flip-flop having two inverters each formed of a load element and a driver transistor cross-coupled to each other is connected through access transistors to a bit line pair.
As a representative memory cell of the SRAM, a CMOS type memory cell has been generally known, in which the load element is formed of a P channel MOS transistor and the driver transistor and the access transistor are formed of N channel MOS transistors. The CMOS type memory cell has small current consumption, and because of the characteristics particular to CMOS, has superior static noise margin (hereinafter also referred to as SNM) and superior soft error immunity.
As other representative memory cells of the SRAM, a high-resistance load type memory cell in which the load element is formed of a high resistance element of polysilicon, and a P channel TFT load type memory cell in which the load element is formed of a P channel thin film transistor (hereinafter also referred to as a P channel TFT) of polysilicon are also known. The high resistance load type memory cell and the P channel TFT load type memory cell have four bulk transistors per one memory cell, and therefore, these are advantageous in that the cell area can be made smaller than the CMOS type memory cell that includes six bulk transistors.
Here, “bulk transistor” refers to a transistor formed in a silicon substrate, as opposed to a thin film element formed on the substrate such as the P channel TFT or the resistance element formed of polysilicon.
Further, as an SRAM that meets the demand for lower voltage, Japanese Patent Laying-Open No. 7-57476 discloses an SRAM in which the access transistor is formed of a P channel MOS transistor. This makes the gate-source voltage of the access transistor equal to a power supply voltage, and hence, decrease in cell current resulting from the lower voltage can be prevented and satisfactory operation under the low voltage is ensured.
Recently, size and power consumption of electronic devices have been made smaller and smaller. Accordingly, smaller size and smaller power consumption have been required of the semiconductor devices. Power consumption is in proportion to a square of power supply voltage, and hence, it is effective to lower the power supply voltage to reduce power consumption. Thus, a semiconductor memory device having high performance that can operate satisfactorily even under a low voltage has been desired.
Here, a “low voltage” generally refers to a voltage lower than 3V, and in these days, the power supply voltage has been decreased from 3.3V that has been widely used conventionally to 2.5V and further down to 1.8V.
In view of the challenge above, in an SRAM used under a low voltage, the above described CMOS type memory cell has been employed. The reason for this is as follows. In the conventional high resistance load type memory cell and P channel TFT load type memory cell, such load elements have small current drivability, and hence, SNM is small. Therefore, operation under a low voltage is instable. On the contrary, the CMOS type memory cell has large SNM because of the CMOS characteristic, and the CMOS inverter operates stably even under a low voltage. Therefore, with the current trend of lowering the voltage, the conventional high resistance load type memory cell or P channel TFT load type memory cell described above is seldom employed, and CMOS type memory cells are dominant.
When the voltage further lowers, however, it becomes difficult even for the conventional CMOS type memory cell as described above to operate satisfactorily. Specifically, in the CMOS type memory cell, the potential of a storage node becomes lower than the power supply potential, which is a low voltage, because of the threshold voltage of the access transistor formed of the N channel MOS transistor, and it becomes impossible to turn on the driver transistor.
Here, it may be possible to lower the threshold voltage of the N channel MOS transistor. Lower threshold voltage, however, leads to an increased leakage current, and the current consumption would rather be increased.
The SRAM described in Japanese Patent Laying-Open No. 7-57476 mentioned above is considered to be a useful solution to the problem, as it does not cause potential lowering at the storage node. Recently, however, a semiconductor memory device having lower power consumption as well as smaller size to enable compact and portable electronic equipment has been strongly desired.
When the size of a semiconductor device is reduced, it naturally follows that the amount of charges stored in the memory cell decreases. Therefore, it is also important to prevent generation of a soft error that tends to occur as the semiconductor memory device is reduced in size.